Neuromorphic Computing

# Neuromorphic Computing

Neuromorphic computing is an approach to processor design that models the architecture and dynamics of biological neural circuits. Rather than the clock-driven, von Neumann architecture that separates memory and computation, neuromorphic systems use networks of artificial neurons and synapses that process information through asynchronous spikes, store data locally at each synaptic connection, and activate only when needed. The goal is energy efficiency at the intersection of sensing, inference, and adaptive learning that current digital hardware cannot match.

## The von Neumann bottleneck

Conventional processors (CPUs, GPUs, even TPUs) execute instructions sequentially or in batch parallel, shuttle data repeatedly between a central processing unit and separate memory banks, and run on a global clock that keeps all components synchronised even when most are idle. This architecture is fast and general-purpose. It is also energy-intensive: the memory-to-processor data movement alone accounts for the majority of power in modern deep learning inference.

The human brain runs on roughly 20 watts, processes sensory streams in real time, and learns continuously from sparse reward signals. A comparable workload on a GPU cluster consumes kilowatts. That energy gap is the central motivation for neuromorphic computing.

## Core principles

**Spiking neural networks (SNNs).** Biological neurons communicate through discrete electrical pulses called action potentials, or spikes, rather than continuous-valued activations. In a spiking network, a neuron only fires when its integrated input crosses a threshold, and only then does it consume computation energy. Periods of inactivity are truly free, unlike a GPU executing floating-point operations on zeros.

**In-memory computation.** Neuromorphic chips co-locate computation and memory at the synapse. Weights are stored in resistive memory elements (phase-change memory, memristors, SRAM cells) directly at the connection point. Data does not travel to a central unit; the multiply-accumulate operation happens where the weight lives.

**Asynchronous event-driven operation.** Without a global clock, components activate only in response to incoming spikes. This enables extremely low idle power and high energy efficiency for sparse, real-world sensor data.

**Spike-timing dependent plasticity (STDP).** Biological synapses strengthen or weaken based on the relative timing of pre- and post-synaptic spikes. STDP and related local learning rules allow neuromorphic systems to adapt on-chip without requiring backpropagation through the whole network, which is impossible to compute locally.

## Hardware implementations

| System | Developer | Scale | Key feature |
|---|---|---|---|
| TrueNorth | IBM | 4,096 cores, 1M neurons, 256M synapses | Ultra-low power (70 mW); pattern recognition |
| Loihi / Loihi 2 | Intel | 1M neurons (Loihi 2) | On-chip learning; programmable learning rules |
| BrainScaleS | Heidelberg Univ. | Accelerated time (10,000x) | Physical neuron emulation; analogue |
| SpiNNaker / SpiNNaker 2 | Manchester Univ. | Up to 1B neurons (SpiNNaker 2) | Real-time neural simulation; ARM cores |
| Tianjic | Tsinghua Univ. | Hybrid SNN+ANN | First chip demonstrated on autonomous bicycle |

Intel's Loihi line is among the most actively developed for practical inference tasks. Intel claims Loihi 2 runs keyword spotting at roughly 1,000 times lower energy per inference than an equivalent neural network on an embedded GPU.

## Current capabilities and limitations

Neuromorphic chips excel at sparse, event-driven workloads: keyword detection in always-on microphones, gesture recognition from event cameras, anomaly detection in industrial sensor streams. They are not yet competitive with GPUs or TPUs for dense matrix operations like training large language models or running transformer inference, where the highly regular data movement of standard architectures is an advantage.

The key unsolved challenges:
- **SNN training**: backpropagation does not apply directly to spiking networks; surrogate gradient methods exist but are less mature than standard deep learning training
- **Toolchain immaturity**: no equivalent of PyTorch-level abstraction for neuromorphic programming
- **Density and interconnect**: biological brains achieve synaptic density through three-dimensional wiring that silicon wafers cannot replicate
- **Precision**: analogue neuromorphic circuits are subject to device variation; digital designs recover precision at the cost of area

## Why it matters beyond power efficiency

Neuromorphic computing is closely tied to the development of event cameras, which output spikes rather than frames, and to embodied robotics, where tight sensor-to-actuator loops must operate under strict power budgets. Edge inference for always-on devices (wearables, implantable medical devices, autonomous sensors) represents the near-term deployment window. Long-term, neuromorphic principles may prove necessary for AI systems that learn continuously from their environment without centralised retraining, a capability conventional deep learning systems do not yet have in deployable form.

Neuromorphic computing

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