Sequential Silicon Stacking: Can We Extend Moore's Law by Building Up, Not Out?

## The Floorplan Problem

For six decades, the semiconductor industry has been fighting physics by shrinking transistors laterally. Smaller processes, smaller features, tighter gates. But as we approach the atomic scale, the returns are diminishing. The next frontier isn't width — it's height.

## What Illinois Researchers Have Done

A team at the University of Illinois has demonstrated a new fabrication technique: sequential silicon stacking. Instead of packaging separate dies side by side (2.5D) or using through-silicon vias (3D stacking with TSVs), their approach builds active transistor layers **directly on top of each other** on the same die.

The key innovation is a low-temperature deposition process that doesn't damage the lower layers. Traditional silicon processing requires temperatures that would destroy previously fabricated transistors. The Illinois team's process operates below 400°C, making sequential stacking viable for the first time at commercial density.

## TSMC, Intel, and Samsung Are Watching

All three major foundries are exploring 3D stacking paths. TSMC's SoIC, Intel's Foveros Direct, Samsung's X-Cube — these are all forms of 3D integration. But the Illinois approach is different: it enables true sequential fabrication rather than post-hoc die bonding. That means three, four, even five layers of active logic, each optimized for different functions.

Imagine a chip where one layer handles power delivery, another handles memory (SRAM), and a third runs high-performance logic — all fabricated monolithically.

## The Numbers That Matter

*   Potential density improvement: 3-5x without node shrinks
*   Power reduction from shorter interconnects: up to 40%
*   Thermal management remains the primary challenge — stacking generates exponentially more heat per unit volume
*   Yield: each additional layer adds defect probability, potentially killing economic viability

## What This Actually Means

Moore's Law, as a predictor of transistor count doubling, has been "dead" in its original formulation for years. What keeps it on life support is packaging innovation. Sequential stacking is the most promising packaging innovation since chiplets. If it reaches commercial viability in the 2030s, it could extend transistor scaling for another decade.

For engineers: this isn't something you'll see in a laptop next year. The first applications will be in HPC and AI accelerators, where the power budget and volume justify the complexity. But the trajectory is set. The third dimension is opening up.

Sequential Silicon Stacking: Can We Extend Moore's Law by Building Up, Not Out?

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