Silicon Photonics: Why AI Datacenters Are Betting on Light but Copper Isn't Done Yet

The bottleneck has shifted. For the past decade, the dominant constraint in computing was raw compute — more transistors, faster clocks, bigger die. That's still true at the chip level. But as AI training clusters grew to hundreds of thousands of GPUs, a different problem became the critical path: moving data between chips.

Electrical copper interconnects can't scale fast enough. At 800 Gbps per link — and next-generation systems pushing well beyond that — copper cables generate heat, require active signal conditioning, and hit physical limits inside the rack. Silicon photonics offers a different path: replace electrons with photons for communication and get much higher bandwidth over longer distances at dramatically lower power per bit.

## How It Actually Works

Silicon photonics integrates optical components — modulators, waveguides, photodetectors, and in some designs, lasers — directly onto a silicon chip using CMOS-compatible fabrication. The waveguides confine light inside the chip, routed by etched silicon structures. A Mach-Zehnder modulator or ring resonator converts electrical data signals into modulated optical pulses. On the receiving side, a germanium photodetector converts light back to electrical current.

The appeal is real: TSMC and Intel's foundries can, in principle, manufacture photonic components on the same lines as conventional logic. The economics scale differently from bespoke optical components.

The engineering reality is messier.

## The Problems That Slow This Down

The most persistent issue is the laser itself. Silicon has an indirect bandgap, which means it can't efficiently emit light. Every silicon photonics chip needs either an external laser attached via fiber coupling, or a heterogeneous integration approach where III-V semiconductors like InP or GaAs are bonded onto silicon. Both options add cost and manufacturing complexity.

Coupling losses at the chip edge are significant. When light transitions from fiber to waveguide, efficiency can drop below 50% depending on the coupling approach. Thermal sensitivity creates another headache: ring resonators shift wavelength with temperature, requiring active control that adds power overhead, partially eating into the efficiency gains you were trying to capture.

These are engineering problems, not physics barriers. Progress is real. Intel's Silicon Photonics division has been shipping 100G transceivers since 2016 and now offers 400G units in volume — actual products, actual revenue. Ayar Labs makes optical I/O chiplets targeting 4 Tbps per chiplet to replace electrical I/O at the package level. Lightmatter built Passage, a photonic interconnect fabric designed to connect AI accelerators inside a rack.

## What the Numbers Look Like

A copper DAC cable at 800 Gbps consumes roughly 5 to 10 W in signal conditioning electronics. A comparable silicon photonics link can manage 1 to 3 W per direction over much longer distances without amplification. At rack scale, the difference is modest. At a 100,000-GPU cluster, it compounds into real infrastructure cost and cooling budget.

The comparison isn't perfectly fair — optical transceivers carry cost and integration overhead that copper doesn't. At short intra-rack distances, copper remains cheaper and sufficient. At inter-rack and inter-pod distances, photonics wins decisively on bandwidth-per-watt, which is why every major hyperscaler already uses optical transceivers for cross-rack communication. The active question is whether photonics moves closer to the silicon: into the package, eventually into the chiplet stack itself.

## The Honest Timeline

In-package optical I/O is a genuine near-term target. DARPA's CHIPS program, Intel's co-packaged optics work, and multiple startups have working silicon. Commercial deployment at volume is still 3 to 5 years out — though that estimate has been "3 to 5 years out" for most of the last decade, which says something about the actual difficulty.

On-chip optical computation — replacing transistors with photonic logic gates — is much further away and possibly not the right frame. Optical logic is difficult to scale, and the nonlinear materials required are still mostly research-grade. The realistic near-term value of photonics is for communication, not arithmetic.

For AI infrastructure, that's actually enough. The energy bottleneck in large training runs isn't only compute. Moving activations and gradients between chips at lower power is a real win, independent of whether photons ever do a multiply-accumulate operation. Getting the interconnect right is where the engineering leverage is right now.

Silicon Photonics: Why AI Datacenters Are Betting on Light but Copper Isn't Done Yet

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